1. Field Of The Invention
The present invention relates to a new contact process interconnect poly-crystal silicon layer, and more particularly, to a process that could reduce dramatically the voltage drop between poly-crystal silicon layer. Their advantages include not only to improve the interface quality of Poly-Si/SiO2 but also do not increase its process complexity and its mask number during the fabrication of poly-crystal silicon thin-film SRAM.
2. Description Of The Prior Art
The structure of poly-crystal silicon thin-film SRAM (as shown in FIG. 1) includes character-line signal (11) and bit-line signal (12). Two junctions of N1, N2 (the contact between poly-crystal silicon layer) are mainly used to connect the Access Transistor Q1,Q2, Driving Transistor Q3,Q4 ,the TFT load Q5, Q6 and the gate of another transistor set. This junction quality will directly influence the whole characteristics of SRAM cell.
The conventional contact process interconnect poly-crystal silicon layer as shown in FIG. 2. After the deposition of the gate 21 (Poly3) of poly-crystal silicon, its upper side will be deposited by a dioxide layer 22 then by a 800.degree. C. high-temperature process to make this dioxide layer 22 more uniform, as shown in FIG. 2A. After that, defining a contact window 23 from the gate of poly-crystal silicon, as shown in FIG. 2B and FIG. 2C. Next, the thin-film channel layer 24 (Poly4) of poly-crystal silicon will again be deposited as shown in FIG. 2D. Finally, the ion implantation of channel layer and source 241, drain 242 occurs, as shown in FIG. 2E. By way of contact window 23, the poly3 and poly4 will link together and form a contact between poly-crystal silicon layer.
This conventional method has some inevitable drawbacks. First, considering the contact section of poly-crystal silicon layer, a PN junction diode is formed due to poly3 is N+, poly4 is P+. When decreasing the device size or lowering its operation voltage, the voltage drop ratio of junction diode will increase and that would deteriorate the device characteristics. Secondly, it is necessary to remove the photo-resist when define the contact window for its gate layer is covered by a dioxide layer. Therefore, the interface of Poly-Si/SiO2 will have more interface states which adversely effect device characteristics such as larger leakage current (Ioff), shift of threshold voltage (Vt-shift), decreasing of subthreshold swing, etc.
Based on the above description, the junction voltage drop ratio will be more obvious by this conventional method when decrease the device size or operation voltage, so the device characteristics deteriorate more seriously. Besides, the leakage current will be a major consideration when the IC with more integrated circuits. This conventional method have more interface states so that increase more leakage current means more power consumption and therefore the power dissipation is more difficult.